1. Technical Field of the Invention
The present invention relates to a control method and device for random access memory (RAM) devices, and particularly to a method and device for controlling bit line isolation circuitry for a dynamic random access memory (DRAM) device.
2. Background of the Invention
There are two known types of semiconductor memory, one referred to as volatile memory and the other referred to as non-volatile memory. In volatile memories the stored data is lost when the power supply is removed from the semiconductor device. A non-volatile memory, on the other hand, retains the data stored for extended periods after the power supply to the device has been removed. In a computer or related systems, non-volatile memory is used for long-term storage of programs and data which seldom or never changes, and volatile memory devices are used for the short-term storage of program instructions and data during the execution of a program.
Volatile memory devices may be divided into two categories. Static Random Access Memory (SRAM) consists of flip-flop latches such that each SRAM latch maintains a bit of data so long as power is provided to the SRAM. In dynamic memories, a charge representing a data bit is stored on a capacitor.
The core of a DRAM is typically partitioned into arrays or blocks of memory cells, with each array including a plurality of rows of memory cells and with the cells in each row being connected to a respective one of a plurality of word lines. Memory cells in each column of cells in an array are connected to a respective one of a plurality of bit lines. Bit lines are grouped in pairs such that when data from a memory cell is read onto a first bit line of a bit line pair, the second bit line of the bit line pair is provided with a voltage level that is representative of a signal between a low logic level and a high logic level, relative to the amount of charge that can be placed thereon by a charge stored in a memory cell. This difference in voltage levels between the bit lines of the bit line pair is the differential to which an associated sense amplifier operatively responds.
Sense amplifiers are typically connected to the bit lines of dynamic memory to sense the small change in potential appearing on the bit lines following a memory cell read operation and to drive the bit lines to the appropriate full reference voltage level, such as Vdd or Vss. Once the sense amplifier drives the bit line to the full reference voltage level, the memory cell from which data was read is refreshed with the full reference voltage signal appearing on the bit line.
Sense amplifiers are operatively connected to a pair of bit lines from one or more memory arrays. Pass and/or transmission gates are employed between the sense amplifiers and the pairs of bit lines from adjacent memory arrays connected to the sense amplifier, in part to limit the capacitance appearing on the bit lines when the sense amplifiers are active, thereby decreasing the time necessary to perform a memory cell read and associated refresh operation. The pass/transmission gates additionally allow the bit lines of the selected bit line pair to incur a slight delay relative to the sense amplifier output nodes as the output nodes are being driven to full reference voltage levels, thereby increasing the speed at which the sense amplifier senses the charge differential of the bit line pair and drives its output nodes. To ensure that the bit lines may be driven to full Vdd and Vss levels, some random access memory designs employ a CMOS transmission gate in which an n-channel transistor and a p-channel transistor are connected in parallel to each other.
Conventional DRAM cells employ a single transistor architecture wherein the memory cell comprises a storage capacitor having a first terminal connected to a reference voltage, such as Vss, and a second terminal connected to a pass gate transistor. The pass gate transistor serves to transport charge to the storage capacitor, and also to read the charged or uncharged state of the storage capacitor. The gate electrode of the pass gate transistor is tied to a word line decode signal and the drain electrode thereof is connected to a bit line. Data is stored in the memory cell as a charge on the storage capacitor. However, because data is stored in a dynamic memory cell as a charge on a capacitor and because memory cells experience leakage current either from the storage capacitor or the pass gate transistor, the stored charge in a dynamic memory cell, particularly a stored charge representing a high logic level, decays over time.
Dynamic memories are created in a number of ways. Dynamic memories that are available as stand-alone, off-the-shelf memory chips are typically fabricated by a process which is specifically tailored to provide optimal DRAM performance. Dynamic memories that are embedded within an integrated circuit chip, however, are commonly fabricated by a process that is not tailored for optimal DRAM performance, but is instead tailored to provide optimal chip-wide performance, such as a process that is suited for size and/or speed considerations. As such, dynamic memories that are embedded within an integrated circuit chip having other circuitry, such as an application specific integrated circuit (ASIC) chip or a microprocessor chip, incur complications and limitations that are not experienced in dynamic memories fabricated by a DRAM-tailored process.
For instance, semiconductor fabrication processes that are tailored for overall performance of an ASIC typically utilize thinner gate oxides relative to gate oxide thicknesses in DRAM-tailored processes. In addition, DRAM-tailored designs typically utilize back gate biasing which is not necessarily employed in ASIC designs. These and other differences lower the threshold voltage of the transistors on the ASIC chip relative to threshold voltages on a chip tailored for optimal DRAM performance. Consequently, for a given gate-source voltage (Vgs), the sub-threshold leakage current for a transistor in an ASIC chip will be greater than a sub-threshold leakage current for a transistor in an integrated circuit fabricated by a DRAM-tailored process. This increase in leakage current for a transistor in an ASIC process is of a particular concern for embedded DRAM devices. Because data is stored in a dynamic memory cell by a stored charge and dynamic memory storage capacitors are typically quite small to achieve relatively high density, a dynamic memory cell may be relatively quickly discharged if sub-threshold leakage currents are not sufficiently controlled, thereby potentially corrupting the data stored in the memory device.
Accordingly, there is a need for a device and method for maintaining sub-threshold leakage current levels associated with memory cells of embedded dynamic memory devices within acceptable limits, taking into consideration memory speed, size constraints and robustness of operation for the embedded dynamic memory device.